In-browser fault sim · no install

Inject faults. Climb the leaderboard.

A gamified fault simulation lab for VLSI students. Stuck-at, transition, IDDQ — inject them, detect them, race up the coverage leaderboard. No install, no license server.

+12 ranks todayClimbed the LB
Platform

A real fault lab, in a tab.

The same fault models you'll use in industry, with a UI that turns dry simulations into something you'll actually want to run.

Real fault models

Stuck-at, transition delay, IDDQ, and bridge faults — all implemented in a fast in-browser engine. No toy simulator, no hand-waving.

Live waveform

Watch the simulation tick. Pin-level waveforms update as the simulator runs, so you can see which transition detected which fault.

Coverage leaderboard

Weekly challenges, monthly tournaments, and an always-on leaderboard. The fastest path to high coverage is your name at the top of the chart.

Import your netlist

Drop in a synthesized Verilog netlist, pick a design from the library, or start from one of the curated challenges. Either way, you're simulating in 60 seconds.

Pattern optimization

The simulator compacts your test set as you go — dropping redundant patterns, marking untestable faults, and reporting the minimal pattern count.

Weekly challenges

Each Monday, a new design with a hidden fault set drops. The fastest solver with the highest coverage takes the weekly rank. Real designs, real patterns.

TRY IT YOURSELF

Run a fault sim on a tiny design

module add4(input [3:0] a, b, output [3:0] sum, output cout);
  assign {cout, sum} = a + b;
endmodule

// inject: stuck-at-0 on add4.b[2]
Takes about 2 seconds in your browser.
Patterns simulated16
Total faults36
Detected34
Undetectable (redundant)2
Stuck-at coverage94.4%

A toy example — the real engine runs against your uploaded netlist with thousands of faults, transition delay, IDDQ, and bridge models. Try it free with your own design.

Pricing

Free for students. Fair for everyone else.

No per-sim fees, no premium challenges, no "buy credits to enter this contest."

Student

For verified students at any level.
$0/mo
free for verified students
  • All fault models
  • Weekly challenges
  • Live waveform
  • Leaderboard access
Verify & start

Classroom

For instructors running a course or lab section.
$6/student/semester
annual billing · min 10 students
  • Everything in Pro
  • Private classroom
  • Custom challenges
  • Aggregate analytics
  • LTI integration
Set up a class
FAQ

Common questions, honest answers.

Is the simulator actually accurate?

Yes. The fault models (stuck-at, transition, IDDQ, bridge) match the textbook definitions. Coverage numbers are real and reproducible. We round-trip patterns with commercial tools for verification — if our numbers don't match, we want to know.

How big a design can I simulate?

Up to ~5,000 gates on the free Student plan, up to 50,000 gates on Pro. Larger designs work but performance varies by browser and machine. We are honest about these limits; we don't fake larger numbers.

Can I import my own netlist?

Yes. Drop in a synthesized Verilog netlist (.v) and the simulator parses it. The free plan supports up to 1,000-gate designs; Pro supports up to 50,000 gates.

Are the leaderboard names real?

Yes — every row is a real student who completed the challenge. We use anonymous IDs (student-7af2) by default; nobody's real name is shown unless they opt in. There are no seed accounts and no fake ranks to fill the chart.

How is the student discount verified?

Through our education partner — a one-time check using your school email or enrollment document. The free plan renews automatically as long as you're a student.

What about tournament prizes?

Honest prizes, honestly listed. Mostly swag (lab notebooks, a textbook stipend, an oscilloscope sponsorship for the top-three's school). The point is the rank, not the merch — and we never inflate the prize list to make a banner look bigger.

Inject your first fault. Race the leaderboard.

Free for students. Free to try for everyone else. No install, no license server, no fake numbers.